Storage device and an operating method of the storage device

ABSTRACT

An operation method of a storage device includes receiving a request; performing an operation corresponding to the received request; generating response data corresponding to the performed operation wherein the response data includes information on the performed operation; and outputting the response data. Status information is added to and output with the response data, wherein the status information includes information on a status of the storage device.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. §119 to Korean PatentApplication No. 10-2014-0035144 filed Mar. 26, 2014, in the KoreanIntellectual Property Office, the disclosure of which is incorporated byreference herein in its entirety.

TECHNICAL FIELD

The inventive concept described herein relates to a storage device andan operation method thereof.

DISCUSSION OF RELATED ART

A storage device may store data according to a control of a host device,such as a computer, a smart phone, or a tablet. The storage device mayinclude a device for storing data on a magnetic disk, such as a harddisk drive, or a semiconductor memory, such as a solid state drive or amemory card. The semiconductor memory may be a nonvolatile memory.

Nonvolatile memories may include a read only memory (ROM), aprogrammable ROM (PROM), an electrically programmable ROM (EPROM), anelectrically erasable and programmable ROM (EEPROM), a flash memory, aphase-change random access memory (PRAM), a magnetic RAM (MRAM), aresistive RAM (RRAM), a ferroelectric RAM (FeRAM), etc.

An operation speed of the host device that communicates with the storagedevice may be increased due to improvements in semiconductor fabricatingtechnology. Accordingly, the size of contents that the storage device orthe host device of the storage device utilizes may be increased.

SUMMARY

An exemplary embodiment of the inventive concept provides an operationmethod of a storage device which includes a nonvolatile memory and amemory controller configured to control the nonvolatile memory, theoperation method comprising receiving a request; performing an operationcorresponding to the received request; generating response datacorresponding to the performed operation, wherein the response dataincludes information on the performed operation; and outputting theresponse data, wherein status information is added to and output withthe response data, wherein the status information includes informationon a status of the storage device.

In an exemplary embodiment of the inventive concept, collection of thestatus information is independent of the received request and theperformed operation.

In an exemplary embodiment of the inventive concept, the response dataand the status information are transferred using a format of UniversalFlash Storage Protocol Information Unit (UPIU).

In an exemplary embodiment of the inventive concept, the statusinformation is transferred using at least one field of 16^(th) to31^(st) fields of a response UPIU.

In an exemplary embodiment of the inventive concept, the statusinformation is transferred using at least one field of 4^(th) to 7^(th),9^(th), and 20^(th) to 31^(st) fields of a data out UPIU format.

In an exemplary embodiment of the inventive concept, the statusinformation is transferred using at least one field of 20^(th) to31^(st) fields of a ready to transfer UPIU.

In an exemplary embodiment of the inventive concept, the statusinformation is transferred using at least one field of 20^(th) to31^(st) fields of a task management response UPIU.

In an exemplary embodiment of the inventive concept, the statusinformation is transferred using at least one field of 28^(th) to31^(st) fields of a query response UPIU.

In an exemplary embodiment of the inventive concept, the statusinformation is transferred using at least one field of 16^(th), 17^(th),and 20^(th) to 27^(th) fields of a query response UPIU.

In an exemplary embodiment of the inventive concept, the statusinformation is transferred using at least one field of 16^(th) to19^(th) and 24^(th) to 27^(th) fields of a query response UPIU.

In an exemplary embodiment of the inventive concept, the statusinformation is transferred using at least one field of 16^(th) to22^(nd) and 24^(th) to 27^(th) fields of a query response UPIU.

In an exemplary embodiment of the inventive concept, the statusinformation is transferred using at least one field of 13^(th) to27^(th) fields of a query response UPIU.

In an exemplary embodiment of the inventive concept, the statusinformation is transferred using at least one field of 12^(th) to31^(th) fields of a NOP IN UPIU.

In an exemplary embodiment of the inventive concept, the statusinformation includes power-control information of the storage device.

In an exemplary embodiment of the inventive concept, the statusinformation further includes information on a time when the storagedevice enters a power-saving mode.

An exemplary embodiment of the inventive concept provides a storagedevice comprising a nonvolatile memory; and a memory controllerconfigured to control the nonvolatile memory, wherein the memorycontroller is further configured to collect status information includinginformation on a status of the nonvolatile memory or the memorycontroller, and wherein if an access request is received from anexternal device, the memory controller is configured to perform theaccess request, add the status information to response data including anexecution result of the access request to generate first data, andoutput the first data to the external device.

An exemplary embodiment of the inventive concept provides a computingsystem comprising a storage device; and a host device configured totransmit a request to the storage device to control the storage device,write data at the storage device or read data from the storage device,wherein the storage device is configured to collect status informationincluding information on a status of the storage device, and wherein thestorage device is further configured to receive the request, perform thereceived request, add the status information to response data includingan execution result of the received request to generate first data, andoutput the first data to the host device.

In an exemplary embodiment of the inventive concept, the storage deviceis further configured to insert a first type of status information at afirst location in a data format including the response data, and thehost device is further configured to extract the first type of statusinformation from the first location of the data format.

In an exemplary embodiment of the inventive concept, the storage deviceis further configured to insert the status information and flaginformation indicating a type of the status information in a data formatincluding the response data, the host device is further configured toextract the status information using the flag information of the statusinformation, and the flag information is inserted at a predeterminedlocation in the data format.

In an exemplary embodiment of the inventive concept, the storage deviceis further configured to insert the status information and mapinformation indicating a location and a type of the status informationin a data format including the response data, the host device is furtherconfigured to extract the status information using the map information,and the map information is inserted at a predetermined location in thedata format.

An exemplary embodiment of the inventive concept provides a method ofoperating a storage device collecting status information of the storagedevice; receiving a request to perform an operation with a memory of thestorage device; performing the operation in response to the request andgenerating operation related data; accessing the status information andcombining the status information with the operation related data; andoutputting the combination of the status information and the operationrelated data in a first data format.

In an exemplary embodiment of the inventive concept, the collecting ofthe status information and the combining of the status information withthe operation related data is performed in a controller of the storagedevice.

In an exemplary embodiment of the inventive concept, the first dataformat includes UPIU.

In an exemplary embodiment of the inventive concept, the memory includesa nonvolatile memory.

In an exemplary embodiment of the inventive concept, the statusinformation is power related.

BRIEF DESCRIPTION OF THE FIGURES

The above and other features of the inventive concept will become moreapparent by describing exemplary embodiments thereof with reference tothe accompanying figures, in which:

FIG. 1 is a block diagram illustrating a storage device according to anexemplary embodiment of the inventive concept;

FIG. 2 is a flow chart illustrating an operation method of a storagedevice according to an exemplary embodiment of the inventive concept;

FIG. 3 shows a format of data that a storage device outputs, accordingto an exemplary embodiment of the inventive concept;

FIGS. 4 to 6 show exemplary embodiments of the inventive concept inwhich status information is included in data output from a storagedevice;

FIG. 7 shows a format of data that a storage device outputs, accordingto an exemplary embodiment of the inventive concept;

FIG. 8 shows a format of data that a storage device outputs, accordingto an exemplary embodiment of the inventive concept;

FIG. 9 shows a format of data that a storage device outputs, accordingto an exemplary embodiment of the inventive concept;

FIG. 10 shows a format of data that a storage device outputs, accordingto an exemplary embodiment of the inventive concept;

FIGS. 11 to 19 show 12th to 27th fields shown in FIG. 10, according toexemplary embodiments of the inventive concept;

FIG. 20 shows a format of data that a storage device outputs, accordingto an exemplary embodiment of the inventive concept;

FIG. 21 is a block diagram illustrating a memory controller according toan exemplary embodiment of the inventive concept;

FIG. 22 is a block diagram illustrating a nonvolatile memory accordingto an exemplary embodiment of the inventive concept;

FIG. 23 is a circuit diagram illustrating a memory block according to anexemplary embodiment of the inventive concept;

FIG. 24 is a circuit diagram illustrating a memory block according to anexemplary embodiment of the inventive concept;

FIG. 25 is a block diagram illustrating a storage device according to anexemplary embodiment of the inventive concept; and

FIG. 26 is a block diagram illustrating a computing device according toan exemplary embodiment of the inventive concept.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Exemplary embodiments of the inventive concept will be described indetail with reference to the accompanying drawings. The inventiveconcept, however, may be embodied in various different forms, and shouldnot be construed as being limited only to the illustrated embodiments.Unless otherwise noted, like reference numerals denote like elementsthroughout the attached drawings and written description, and thusdescriptions will not be repeated. In the drawings, the sizes andrelative sizes of layers and regions may be exaggerated for clarity.

As used herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise.

It will be understood that when an element or layer is referred to asbeing “on”, “connected to”, “coupled to”, or “adjacent to” anotherelement or layer, it can be directly on, connected, coupled, or adjacentto the other element or layer, or intervening elements or layers may bepresent.

FIG. 1 is a block diagram illustrating a storage device 100 according toan exemplary embodiment of the inventive concept. Referring to FIG. 1,the storage device 100 contains a nonvolatile memory 110 and a memorycontroller 120. The storage device 100 may be a solid state drive, amemory card, or an embedded memory.

The nonvolatile memory 110 performs read, write, and erase operationsaccording to a control of the memory controller 120. The nonvolatilememory 110 may include a flash memory. However, the inventive concept isnot limited thereto. For example, the nonvolatile memory 110 may includeat least one of nonvolatile memories, such as Phase-change random accessmemory (PRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), FerroelectricRAM (FeRAM), and so on.

The memory controller 120 is configured for controlling the nonvolatilememory 110 according to a request of a host device (not shown) oraccording to a predetermined schedule. For example, the memorycontroller 120 controls the nonvolatile memory 110 to perform a read, awrite, or an erase operation. The memory controller 120 informs the hostdevice 100 of a degree of write-progression of write requests.

The memory controller 120 contains an information collection unit 221and an information addition unit 222. The information collection unit221 may collect information on a status of the storage device 100periodically or continuously.

For example, the information collection unit 221 collects information ona power of the storage device 100. In the storage device 100, theinformation collection unit 221 may collect, as status information, atleast one of power consumption of the storage device 100, expected powerconsumption of the storage device 100, information indicating whether acurrent mode of the storage device 100 is a power-saving mode or awake-up mode, information of a time when the storage device 100 entersthe power-saving mode, and information of a time when the storage device100 enters the wake-up mode.

For example, the information collection unit 221 may collect informationon a life time (or, expected life time) of the storage device 100 as thestatus information.

For example, the information collection unit 221 may collect a messagethat the storage device 100 needs to send to a host device (not shown)for accessing the storage device 100. For example, the informationcollection unit 221 may collect, as the status information, a messagefor requesting control of a channel used to communicate with the storagedevice 100 in a power-saving mode, a message for requesting a statuscheck of the storage device 100, and so on.

For example, the memory controller 120 stores a variety of information,which is necessary to control the storage device 100, in registers. Theinformation collection unit 221 may associate the registers withparticular status information of the memory controller 120.

For example, the information collection unit 221 may include acollection module configured to collect status information of thestorage device 100 actively and registers configured to store thecollected status information.

The information addition unit 222 adds status information collected bythe information collection unit 221 to data that the memory controller120 outputs to an external host device. For example, the memorycontroller 120 may receive a variety of requests from the external hostdevice. Based on the input requests, the memory controller 120 performsoperations corresponding to the input requests. Executing the operationscorresponding to the input requests, the memory controller 120 providesthe external host device with data (e.g., response data) includinginformation on the results of the executed operations. The memorycontroller 120 adds the status information to data to be provided to theexternal host device.

In an exemplary embodiment of the inventive concept, at least one of theinformation collection unit 221 and information addition unit 222 may beimplemented with software, hardware, or a combination of hardware andsoftware.

FIG. 2 is a flow chart illustrating an operation method of the storagedevice 100 according to an exemplary embodiment of the inventiveconcept. Referring to FIGS. 1 and 2, in step S110, status information iscollected. For example, the information collection unit 221 may collectstatus information periodically, continuously, or when statusinformation is changed.

In step S120, whether a request is received is determined. If a requestis not received from an external host device (not shown), the storagedevice 100 may not perform an operation using status information. If arequest is received from the external host device, the method proceedsto step S130.

In step S130, the storage device 100 performs an operation according tothe input request. In step S140, the storage device 100 generatesresponse data including operation information and status information.For example, the storage device 100 may produce response data thatcontains information indicating an operation-executed result and statusinformation.

In step S150, the memory controller 120 provides the external hostdevice with the response data including the operation information andthe status information.

In an exemplary embodiment of the inventive concept, a request from theexternal host device may contain a request for writing data at thestorage device 100, a request for reading data from the storage device100, a request for erasing data in the storage device 100, a request forcontrolling the storage device 100, and so on. A request from theexternal host device may be one of requests defined by the communicationstandard between the storage device 120 and the external host device.The request does not have to include a request for status information,in fact it may not. In other words, the storage device 100 receivesnormal requests from the external host device and executes operationsaccording to the normal requests. The storage device 100 provides theexternal host device with normal response data indicatingoperation-executed results. In particular, the storage device 100 maytransmit status information additionally.

The operation S110 of collecting status information is described as itis executed before a request is received from the external host device.However, the inventive concept is not limited thereto. For example, theoperation S110 of collecting status information may be executed after arequest is received from the external host device.

FIG. 3 shows a format of data that the storage device 100 outputs,according to an exemplary embodiment of the inventive concept. In anexemplary embodiment of the inventive concept, the storage device 100may output data according to a format of Universal Flash StorageProtocol Information Unit (UPIU) defined by the Universal Flash Storage(UFS) specification.

Referring to FIG. 3, the storage device 100 outputs a response UPIU. Theresponse UPIU is formed of a plurality of fields. Each field of theresponse UPIU is referred to using a number marked in a box. Each fieldof the response UPIU includes 1-byte data.

A 0^(th) field of the response UPIU includes information on atransaction type. For example, a transaction code assigned to theresponse UPIU is ‘100001b’. A 1^(st) field of the response UPIU containsinformation on a flag. The 1^(st) field may store a data overflow flagindicating that the amount of data the storage device 100 will send isgreater than that of data an external host device requests, a dataunderflow flag indicating that the amount of data the storage device 100will send is smaller than that of data the external host devicerequests, a flag indicating that a buffer offset or a transfer count ofrequested data is abnormal, and so on. A 2^(nd) field of the responseUPIU stores information on a logical unit number (LUN) of a targetdevice, and a 3^(rd) field of the response UPIU includes information ona task tag.

A part (e.g., four bits) of a 4^(th) field of the response UPIU is usedas a status information area SIA, and the rest (e.g., four bits) of the4^(th) field contains information on a command set type. For example,the command set type may include a small computer system interface(SCSI) command set, a UFS specific command set, a vendor specificcommand set, and so on. A 5^(th) field of the response UPIU is used as astatus information area SIA. A 6^(th) field of the response UPIU is aresponse field (denoted as ‘v’). The 6^(th) field may includeinformation indicating whether an operation corresponding to a requestreceived from the external host device succeeds or fails. A 7^(th) fieldof the response UPIU stores information on an SCSI status according tothe SCSI command set.

An 8^(th) field of the response UPIU includes a total length of an ExtraHeader Segment (EHS). A 9^(th) field of the response UPIU stores deviceinformation. 10^(th) and 11^(th) fields of the response UPIU containinformation on the number of valid bytes of a data segment. For example,the 10^(th) field includes a most significant bit (MSB) thereof, and the11^(th) field includes a least significant bit (LSB) thereof.

12^(th) to 15^(th) fields of the response UPIU may include the number ofbytes that the storage device 100 does not send when a data overflowoccurs, the number of bytes that the storage device 100 does not sendwhen a data underflow occurs, and so on. For example, a residual datatransfer count may be found in the 12^(th) to 15^(th) fields.

16^(th) to 31^(st) fields of the response UPIU are used as statusinformation areas SIA.

An end-to-end Cyclic Redundancy Check (CRC) code of a header (shown asHeader E2ECRC in FIG. 3 and many of the following figures) is optionallyadded following the 31^(st) field of the response UPIU. For example, ifa first bit of the 0^(th) field is ‘0’, the end-to-end CRC code of thedata may be omitted (shown as HD=0 in FIG. 3 and many of the followingfigures). In this case, a k^(th) field of the response UPIU may be a32^(nd) field following the 31^(st) field.

The k^(th) field of the response UPIU stores information on lengths ofsense data fields. (k+1)^(th) to (k+19)^(th) fields of the response UPIUare sense data fields and contain additional information on an errorstatus.

An end-to-end CRC code of data (shown as Data E2ECRC in FIG. 3 and manyof the following figures) is optionally added following the (k+19)^(th)field of the response UPIU. For example, if a second bit of the 0^(th)field is ‘0’, the end-to-end CRC code of data may be omitted (shown asDD=0 in FIG. 3 and many of the following figures).

A part of the 4^(th) field, the 5^(th) field, and the 16^(th) to 31^(st)fields of the response UPIU are used as a status information area SIA.Status information may be added as at least one field or at least onebit of the status information area SIA.

In the case status information is added to another field besides thestatus information area SIA, data that is to be sent from the storagedevice 100 to an external host device may be damaged by the statusinformation. Thus, since the status information is added as at least onefield or at least one bit of the status information area SIA in fieldsother than those already including data, the status information may besent to the external host device together with a result of an operationthat the storage device 100 has performed. This use of the statusinformation can increase operation performance of the storage device100. For example, this information can be utilized by the host device todetermine how to control the storage device.

In an exemplary embodiment of the inventive concept, the two or morestatus information may be included in a predetermined location (e.g., afield or a bit) of the status information area SIA according torespective information types. Locations of the two or more statusinformation according to types of the two or more status information maybe in common to the storage device 100 and the external host. A hostdevice receiving a response UPIU may extract the two or more statusinformation from a predetermined location of the status information areaSIA.

For example, as illustrated in FIG. 4, first status information SI1 maybe included in a 16^(th) field of the response UPIU, and second statusinformation SI2 may be included in a 17^(th) field of the response UPIU.Third status information SI3 may be included in an 18^(th) field of theresponse UPIU, and fourth status information SI4 may be included in a19^(th) field of the response UPIU. In the case the storage device 100provides the second status information SI2, it adds the second statusinformation SI2 to the 17^(th) field. In the case the storage device 100does not provide the second status information SI2, it may empty the17^(th) field.

In an exemplary embodiment of the inventive concept, the two or morestatus information may be included in the status information area SIA.The two or more status information may be provided together with flagdata indicating respective information type. In this case, locations ofthe two or more information are not determined according to the types ofthe two or more status information, and locations of the flag data arepredetermined. For example, a first bit of each field of the statusinformation area SIA is set to include flag data, and remaining bits ofthe status information area SIA may be set to include status informationassociated with the flag data. The external host device may extract thestatus information based on the flag data.

For example, as illustrated in FIG. 5, 16^(th) to 19^(th) fields of theresponse UPIU may be set to include status information. At least a firstbit of each of the 16^(th) to 19^(th) fields may be set to include flagdata F. Remaining bits of each of the 16^(th) to 19^(th) fields may beset to include status information SI1 to SI4.

In the event that the storage device 100 is configured to provide firstand second status information SI1 and SI2, it adds flag data Findicating a type of the first status information SI1 to at least thefirst bit of the 16^(th) field and the first status information SI1 tothe remaining bits of the 16^(th) field. The storage device 100 addsflag data F indicating a type of the second status information SI2 to atleast the first bit of the 17^(th) field and the second statusinformation SI2 to the remaining bits of the 17^(th) field.

In the event that the storage device 100 is configured to provide thirdand fourth status information SI3 and SI4, it adds flag data Findicating a type of the third status information SI1 to at least thefirst bit of the 18^(th) field and the third status information SI3 tothe remaining bits of the 18^(th) field. The storage device 100 addsflag data F indicating a type of the fourth status information SI4 to atleast the first bit of the 19^(th) field and the fourth statusinformation SI4 to the remaining bits of the 19^(th) field.

As another example, two or more status information may be included inthe status information area SIA. The two or more status information maybe provided together with status information map data indicating typesof the two or more status information and locations where the two ormore status information is stored. In this case, a size and a locationof the status information map data may be predetermined. Sizes andlocations of the two or more status information may not be limited. Theexternal host device may extract the two or more status informationusing the status information map data.

For example, as illustrated in FIG. 6, 16^(th) to 19^(th) fields of theresponse UPIU may be set to include status information. Statusinformation map data SIM may be included in some bits of the 16^(th)field. Status information SIA corresponding to the status informationmap data SIM may be included in the remaining bits of the 16^(th) fieldand 17^(th) to 19^(th) fields.

FIG. 7 shows a format of data that the storage device 100 outputs,according to an exemplary embodiment of the inventive concept. In anexemplary embodiment of the inventive concept, the storage device 100may output data according to a format of UPIU according to the UFSspecification.

Referring to FIG. 7, the storage device 100 outputs a data out UPIU. Thedata out UPIU is formed of a plurality of fields. Each field of the dataout UPIU is referred to using a number marked in a box. Each field ofthe data out UPIU includes 1-byte data.

A 0^(th) field of the data out UPIU includes information on atransaction type. For example, a transaction code assigned to the dataout UPIU is ‘100010b’. A 1^(st) field of the data out UPIU is a flagfield and is not used in a data out UPIU. A 2^(nd) field of the data outUPIU stores information on a LUN of a target device, and a 3^(rd) fieldof the data out UPIU includes information on a task tag.

4^(th) to 7^(th) fields of the data out UPIU may be used as a statusinformation area SIA.

An 8^(th) field of the data out UPIU includes a total length of an EHS.A 9^(th) field of the data out UPIU is used as a status information areaSIA. 10^(th) and 11^(th) fields of the data out UPIU contain informationon the number of valid bytes of a data segment.

12^(th) to 15^(th) fields of the data out UPIU may include informationon an offset of data, included in a corresponding UPIU, from among alldata to be transmitted. In other words, a data transfer offset.

16^(th) to 19^(th) fields of the data out UPIU include information onthe number of bytes of data to be transmitted via a corresponding UPIU.In other words, a data buffer offset.

20^(th) to 31^(st) fields of the data out UPIU are used as statusinformation areas SIA.

An end-to-end CRC code of a header is optionally added following the31^(st) field of the data out UPIU. For example, if a first bit of the0^(th) field is ‘0’, the end-to-end CRC code may be omitted. In thiscase, a k^(th) field of the data out UPIU may be a 32^(nd) fieldfollowing the 31^(st) field.

The k^(th) field of the data out UPIU and following fields thereof(e.g., k+1 to k+Length−1) may include output data.

An end-to-end CRC code of data is optionally added following output datafields. For example, if a second bit of the 0^(th) field is ‘0’, theend-to-end CRC code of data may be omitted.

The 4^(th) to 7^(th) fields, the 9^(th) field, and the 20^(th) to31^(st) fields of the data out UPIU are used as a status informationarea SIA. Status information may be added as at least one field or atleast one bit of the status information area SIA.

For example, as described with reference to FIG. 4, two or more statusinformation may be included at a predetermined location. As describedwith reference to FIG. 5, two or more status information may be includedtogether with flag data. As described with reference to FIG. 6, two ormore status information may be included together with status informationmap data.

FIG. 8 shows a format of data that the storage device 100 outputs,according to an exemplary embodiment of the inventive concept. In anexemplary embodiment of the inventive concept, the storage device 100may output data according to a format of UPIU according to the UFSspecification.

Referring to FIG. 8, the storage device 100 outputs a ready to transferUPIU. The ready to transfer UPIU is formed of a plurality of fields.Each field of the ready to transfer UPIU is referred to using a numbermarked in a box. Each field of the ready to transfer UPIU includes1-byte data.

A 0^(th) field of the ready to transfer UPIU includes information on atransaction type. For example, a transaction code assigned to the readyto transfer UPIU is ‘110001b’. A 1^(st) field of the ready to transferUPIU is a flag field and is not used in a ready to transfer UPIU. A2^(nd) field of the ready to transfer UPIU stores information on a LUNof a target device, and a 3^(rd) field of the ready to transfer UPIUincludes information on a task tag.

4^(th) to 7^(th) fields of the ready to transfer UPIU may be used as astatus information area SIA.

An 8^(th) field of the ready to transfer UPIU includes a total length ofan EHS. A 9^(th) field of the ready to transfer UPIU is used as a statusinformation area SIA. 10^(th) and 11^(th) fields of the ready totransfer UPIU indicate information on the number of valid bytes of adata segment and are not used in the ready to transfer UPIU.

12^(th) to 15^(th) fields of the ready to transfer UPIU may includeinformation on a start location of data to be transmitted. In otherwords, a data buffer offset.

16^(th) to 19^(th) fields of the ready to transfer UPIU includeinformation on the number of bytes that an external host devicerequests. In other words, a data transfer offset.

20^(th) to 31^(st) fields of the ready to transfer UPIU are used asstatus information areas SIA.

An end-to-end CRC code of a header is optionally added following the31^(st) field of the ready to transfer UPIU. For example, if a first bitof the 0^(th) field is ‘0’, the end-to-end CRC code of the header may beomitted.

The 4^(th) to 7^(th) fields, the 9^(th) field, and the 20^(th) to31^(st) fields of the ready to transfer UPIU are used as a statusinformation area SIA. Status information may be added as at least onefield or at least one bit of the status information area SIA.

For example, as described with reference to FIG. 4, two or more statusinformation may be included at a predetermined location. As describedwith reference to FIG. 5, two or more status information may be includedtogether with flag data. As described with reference to FIG. 6, two ormore status information may be included together with status informationmap data.

FIG. 9 shows a format of data that the storage device 100 outputs,according to an exemplary embodiment of the inventive concept. In anexemplary embodiment of the inventive concept, the storage device 100may output data according to a format of UPIU according to the UFSspecification.

Referring to FIG. 9, the storage device 100 outputs a task managementresponse UPIU. The task management response UPIU is formed of aplurality of fields. Each field of the task management response UPIU isreferred to using a number marked in a box. Each field of the taskmanagement response UPIU includes 1-byte data.

A 0^(th) field of the task management response UPIU includes informationon a transaction type. For example, a transaction code assigned to thetask management response UPIU is ‘100100b’. A 1^(st) field of the taskmanagement response UPIU is a flag field and is not used in a taskmanagement response UPIU. A 2^(nd) field of the task management responseUPIU stores information on a LUN of a target device, and a 3^(rd) fieldof the task management response UPIU includes information on a task tag.

4^(th) to 7^(th) fields of the task management response UPIU may be usedas a status information area SIA.

An 8^(th) field of the task management response UPIU includes a totallength of an EHS. A 9^(th) field of the task management response UPIU isused as a status information area SIA. 10^(th) and 11^(th) fields of thetask management response UPIU indicate information on the number ofvalid bytes of a data segment and are not used in the task managementresponse UPIU.

12^(th) to 19^(th) fields of the task management response UPIU mayinclude information on a task management service response. In otherwords, output parameters 1 and 2. For example, the 12^(th) to 19^(th)fields may include information indicating whether a requested task iscompleted, whether a task is a task that the storage device 100 does notsupport, whether a task fails or succeeds, whether a LUN is correct, andso on.

20^(th) to 31^(st) fields of the task management response UPIU are usedas status information areas SIA.

An end-to-end CRC code of a header is optionally added following the31^(st) field of the task management response UPIU. For example, if afirst bit of the 0^(th) field is ‘0’, the end-to-end CRC code of theheader may be omitted.

The 4^(th) to 7^(th) fields, the 9^(th) field, and the 20^(th) to31^(st) fields of the task management response UPIU are used as a statusinformation area SIA. Status information may be added as at least onefield or at least one bit of the status information area SIA.

For example, as described with reference to FIG. 4, two or more statusinformation may be included at a predetermined location. As describedwith reference to FIG. 5, two or more status information may be includedtogether with flag data. As described with reference to FIG. 6, two ormore status information may be included together with status informationmap data.

FIG. 10 shows a format of data that the storage device 100 outputs,according to an exemplary embodiment of the inventive concept. In anexemplary embodiment of the inventive concept, the storage device 100may output data according to a format of UPIU according to the UFSspecification.

Referring to FIG. 10, the storage device 100 outputs a query responseUPIU. The query response UPIU is formed of a plurality of fields. Eachfield of the query response UPIU is referred to using a number marked ina box. Each field of the query response UPIU includes 1-byte data.

A 0^(th) field of the query response UPIU includes information on atransaction type. For example, a transaction code assigned to the queryresponse UPIU is ‘010110b’. A 1^(st) field of the query response UPIU isa flag field and is not used in a query response UPIU. A 2^(nd) field ofthe query response UPIU is used as a status information area SIA. A3^(rd) field of the query response UPIU includes information on a tasktag.

A 4^(th) field of the query response UPIU is used as a statusinformation area SIA. A 5^(th) field of the query response UPIU includesan original query function value received via a query request UPIU. A6^(th) field of the query response UPIU includes information on anoperation that is executed according to the query request UPIU. A 7^(th)field of the query response UPIU is used as a status information areaSIA.

An 8^(th) field of the query response UPIU includes a total length of anEHS. A 9^(th) field of the query response UPIU includes deviceinformation and is reserved. 10^(th) and 11^(th) fields of the queryresponse UPIU indicate information on the number of valid bytes of adata segment.

12^(th) to 27^(th) fields of the query response UPIU may include avariety of information according to a type of query response UPIU, whichwill be described later. In other words, transaction specific fields.

28^(th) to 31^(st) fields of the query response UPIU are used as statusinformation areas SIA.

An end-to-end CRC code of a header is optionally added following the31^(st) field of the query response UPIU. For example, if a first bit ofthe 0^(th) field is ‘0’, the end-to-end CRC code of the header may beomitted. In this case, a kfth field of the query response UPIU may be a32^(nd) field following the 31^(st) field.

The k^(th) field of the query response UPIU and following fields thereof(e.g., k+1 to k+Length−1) may include output data. For example, datafields may be provided selectively according to a type of a queryresponse UPIU.

An end-to-end CRC code of data is optionally added following output datafields. For example, if a first bit of the 0^(th) field is ‘0’, theend-to-end CRC code of the data may be omitted.

The 2^(nd), 4^(th), 7^(th), and 28^(th) to 31^(st) fields of the queryresponse UPIU are used as a status information area SIA. Statusinformation may be added as at least one field or at least one bit ofthe status information area SIA.

For example, as described with reference to FIG. 4, two or more statusinformation may be included at a predetermined location. As describedwith reference to FIG. 5, two or more status information may be includedtogether with flag data. As described with reference to FIG. 6, two ormore status information may be included together with status informationmap data.

FIG. 11 shows the 12^(th) to 27^(th) fields shown in FIG. 10, accordingto an exemplary embodiment of the inventive concept. In FIG. 11, thereare illustrated 12^(th) to 27^(th) fields of a query response UPIU thatare generated according to a query request UPIU requesting a readdescriptor.

Referring to FIG. 11, the 12^(th) field includes information on anopcode. An opcode associated with a read descriptor may be ‘01h’. The13^(th) field is associated with an opcode and includes the samedescriptor identification number (IDN) as the query request UPIU. The14^(th) field is an index field and includes the same index value as thequery request UPIU. The 15^(th) field is a selector field and includesthe same selector value as the query request UPIU.

The 16^(th) and 17^(th) fields are used as a status information areaSIA. The 18^(th) and 19^(th) fields include information on the number ofbytes returned according to the query request UPIU.

The 20^(th) to 27^(th) fields are used as a status information area SIA.

The query response UPIU associated with the read descriptor may use the16^(th), 17^(th), and 20^(th) to 27^(th) fields as a status informationarea SIA.

FIG. 12 shows the 12^(th) to 27^(th) fields shown in FIG. 10, accordingto an exemplary embodiment of the inventive concept. In FIG. 12, thereare illustrated 12^(th) to 27^(th) fields of a query response UPIU thatare generated according to a query request UPIU requesting a writedescriptor.

Referring to FIG. 12, the 12^(th) field includes information on anopcode. An opcode associated with a write descriptor may be ‘02h’. The13^(th) field is associated with an opcode and includes the samedescriptor identification number (IDN) as the query request UPIU. The14^(th) field is an index field and includes the same index value as thequery request UPIU. The 15^(th) field is a selector field and includesthe same selector value as the query request UPIU.

The 16^(th) and 17^(th) fields are used as a status information areaSIA. The 18^(th) and 19^(th) fields include information on the number ofdescriptor bytes written according to the query request UPIU.

The 20^(th) to 27^(th) fields are used as a status information area SIA.

The query response UPIU associated with the write descriptor may use the16^(th), 17^(th), and 20^(th) to 27^(th) fields as a status informationarea SIA.

FIG. 13 shows the 12^(th) to 27^(th) fields shown in FIG. 10, accordingto an exemplary embodiment of the inventive concept. In FIG. 13, thereare illustrated 12^(th) to 27^(th) fields of a query response UPIU thatare generated according to a query request UPIU requesting readattributes.

Referring to FIG. 13, the 12^(th) field includes information on anopcode. An opcode associated with read attributes may be ‘03h’. The13^(th) field is associated with an opcode and includes the sameattribute identification number (IDN) as the query request UPIU. The14^(th) field is an index field and includes the same index value as thequery request UPIU. The 15^(th) field is a selector field and includesthe same selector value as the query request UPIU.

The 16^(th) though 19^(th) fields are used as a status information areaSIA.

The 20^(th) to 23^(rd) fields include a value of read attributes.

The 24^(th) to 27^(th) fields are used as a status information area SIA.

The query response UPIU associated with the read attributes may use the16^(th) to 19^(th) and 24^(th) to 27^(th) fields as a status informationarea SIA.

FIG. 14 shows the 12^(th) to 27^(th) fields shown in FIG. 10, accordingto an exemplary embodiment of the inventive concept. In FIG. 14, thereare illustrated 12^(th) to 27^(th) fields of a query response UPIU thatare generated according to a query request UPIU requesting writeattributes.

Referring to FIG. 14, the 12^(th) field includes information on anopcode. An opcode associated with write attributes may be ‘04h’. The13^(th) field is associated with an opcode and includes the sameattribute identification number (IDN) as the query request UPIU. The14^(th) field is an index field and includes the same index value as thequery request UPIU. The 15^(th) field is a selector field and includesthe same selector value as the query request UPIU.

The 16^(th) through 19^(th) fields are used as a status information areaSIA.

The 20^(th) to 23^(rd) fields include a value of write attributes.

The 24^(th) to 27^(th) fields are used as a status information area SIA.

The query response UPIU associated with the write attributes may use the16^(th) to 19^(th) and 24^(th) to 27^(th) fields as a status informationarea SIA.

FIG. 15 shows the 12^(th) to 27^(th) fields shown in FIG. 10, accordingto an exemplary embodiment of the inventive concept. In FIG. 15, thereare illustrated 12^(th) to 27^(th) fields of a query response UPIU thatare generated according to a query request UPIU requesting a read flag.

Referring to FIG. 15, the 12^(th) field includes information on anopcode. An opcode associated with a read flag may be ‘05h’. The 13^(th)field is associated with an opcode and includes the same flagidentification number (IDN) as the query request UPIU. The 14^(th) fieldis an index field and includes the same index value as the query requestUPIU. The 15^(th) field is a selector field and includes the sameselector value as the query request UPIU.

The 16^(th) through 22^(nd) fields are used as a status information areaSIA.

The 23^(rd) field includes a flag value.

The 24^(th) to 27^(th) fields are used as a status information area SIA.

The query response UPIU associated with the read flag may use the16^(th) to 22^(nd) and 24^(th) to 27^(th) fields as a status informationarea SIA.

FIG. 16 shows the 12^(th) to 27^(th) fields shown in FIG. 10, accordingto an exemplary embodiment of the inventive concept. In FIG. 16, thereare illustrated 12^(th) to 27^(th) fields of a query response UPIU thatare generated according to a query request UPIU requesting a set flag.

Referring to FIG. 16, the 12^(th) field includes information on anopcode. An opcode associated with a set flag may be ‘06h’. The 13^(th)field is associated with an opcode and includes the same flagidentification number (IDN) as the query request UPIU. The 14^(th) fieldis an index field and includes the same index value as the query requestUPIU. The 15^(th) field is a selector field and includes the sameselector value as the query request UPIU.

The 16^(th) through 22^(nd) fields are used as a status information areaSIA.

The 23^(rd) field includes a flag value.

The 24^(th) to 27^(th) fields are used as a status information area SIA.

The query response UPIU associated with the set flag may use the 16^(th)to 22^(nd) and 24^(th) to 27^(th) fields as a status information areaSIA.

FIG. 17 shows the 12^(th) to 27^(th) fields shown in FIG. 10, accordingto an exemplary embodiment of the inventive concept. In FIG. 17, thereare illustrated 12^(th) to 27^(th) fields of a query response UPIU thatare generated according to a query request UPIU requesting a clear flag.

Referring to FIG. 11, the 12^(th) field includes information on anopcode. An opcode associated with the clear flag may be ‘07h’. The13^(th) field is associated with an opcode and includes the same flagidentification number (IDN) as the query request UPIU. The 14^(th) fieldis an index field and includes the same index value as the query requestUPIU. The 15^(th) field is a selector field and includes the sameselector value as the query request UPIU.

The 16^(th) through 22^(nd) fields are used as a status information areaSIA.

The 23^(rd) field includes a flag value.

The 24^(th) to 27^(th) fields are used as a status information area SIA.

The query response UPIU associated with the clear flag may use the16^(th) to 22^(nd) and 24^(th) to 27^(th) fields as a status informationarea SIA.

FIG. 18 shows the 12^(th) to 27^(th) fields shown in FIG. 10, accordingto an exemplary embodiment of the inventive concept. In FIG. 18, thereare illustrated 12^(th) to 27^(th) fields of a query response UPIU thatare generated according to a query request UPIU requesting a toggleflag.

Referring to FIG. 11, the 12^(th) field includes information on anopcode. An opcode associated with the toggle flag may be ‘08h’. The13^(th) field is associated with an opcode and includes the same flagidentification number (IDN) as the query request UPIU. The 14^(th) fieldis an index field and includes the same index value as the query requestUPIU. The 15^(th) field is a selector field and includes the sameselector value as the query request UPIU.

The 16^(th) through 22^(nd) fields are used as a status information areaSIA.

The 23^(rd) field includes a flag value.

The 24^(th) to 27^(th) fields are used as a status information area SIA.

The query response UPIU associated with the toggle flag may use the16^(th) to 22^(nd) and 24^(th) to 27^(th) fields as a status informationarea SIA.

FIG. 19 shows the 12^(th) to 27^(th) fields shown in FIG. 10, accordingto an exemplary embodiment of the inventive concept. In FIG. 19, thereare illustrated 12^(th) to 27^(th) fields of a query response UPIU thatare generated according to an NOP query request UPIU.

Referring to FIG. 19, the 12^(th) field includes information on anopcode. An opcode associated with the NOP may be ‘00h’. The 13^(th) to27^(th) fields are used as a status information area SIA. A queryresponse UPIU associated with the NOP may use the 13^(th) to 27^(th)fields as a status information area SIA.

FIG. 20 shows a format of data that the storage device 100 outputs,according to an exemplary embodiment of the inventive concept. In anexemplary embodiment of the inventive concept, the storage device 100may output data according to a format of UPIU according to the UFSspecification.

Referring to FIG. 20, the storage device 100 outputs a NOP IN UPIU. TheNOP IN UPIU is formed of a plurality of fields. Each field of the NOP INUPIU is referred to using a number marked in a box. Each field of theNOP IN UPIU includes 1-byte data.

A 0^(th) field of the NOP IN UPIU includes information on a transactiontype. For example, a transaction code assigned to the response UPIU is‘100000b’. A 1^(st) field of the NOP IN UPIU is a flag field and is notused in the NOP IN UPIU. A 2^(nd) field of the NOP IN UPIU is used as astatus information area SIA. A 3^(rd) field of the NOP IN UPIU containsinformation on a task tag.

4^(th) and 5^(th) fields of the NOP IN UPIU are used as a statusinformation area SIA. A 6^(th) field of the NOP IN UPIU containsinformation indicating that the storage device 100 is ready to respondto a request of an external host device. A 7^(th) field of the NOP INUPIU is used as a status information area SIA.

An 8^(th) field of the NOP IN UPIU includes a total length of an EHS. A9^(th) field of the NOP IN UPIU is a device information field. 10^(th)and 11^(th) fields of the NOP IN UPIU indicate information on the numberof valid bytes of a data segment and are not used in the NOP IN UPIU.

12^(th) to 31^(st) fields of the NOP IN UPIU are used as statusinformation areas SIA.

An end-to-end CRC code of a header is optionally added following the31^(st) field of the NOP IN UPIU. For example, if a first bit of the0^(th) field is ‘0’, the end-to-end CRC code of the header may beomitted.

The 2^(nd), 4^(th), 5^(th), 7^(th), and 12^(th) to 31^(st) fields of theNOP IN UPIU are used a status information area SIA. Status informationmay be added as at least one field or at least one bit of the statusinformation area SIA.

For example, as described with reference to FIG. 4, two or more statusinformation may be included at a predetermined location. As describedwith reference to FIG. 5, two or more status information may be includedtogether with flag data. As described with reference to FIG. 6, two ormore status information may be included together with status informationmap data.

In the data formats described with reference to FIGS. 3 to 20, 24^(th)to 31^(st) fields may be used as status information areas SIA in common.Thus, status information may be added as at least one bit or at leastone field of the 24^(th) to 31^(st) fields that the storage device 100outputs.

FIG. 21 is a block diagram illustrating a memory controller 120according to an exemplary embodiment of the inventive concept. Referringto FIG. 21, the memory controller 120 includes a bus 121, a processor122, a RAM 123, an error correcting code (ECC) block 124, a hostinterface 125, a buffer control circuit 126 and a memory interface 127.

The bus 121 may be configured to provide a channel among components ofthe memory controller 120.

The processor 122 controls an overall operation of the memory controller120 and executes a logical operation. The processor 122 communicateswith an external host through the host interface 125. The processor 122stores commands or addresses received via the host interface 125 in theRAM 123. The processor 122 may store data received via the hostinterface 125 in the RAM 123. The processor 122 generates internalcommands and addresses according to commands or addresses stored in theRAM 123 and outputs them via the memory interface 127. The processor 122outputs data stored in the RAM 123 via the memory interface 127. Theprocessor 122 may store data received via the memory interface 127 inthe RAM 123. The processor 122 may output data stored in the RAM 123 viathe host interface 125 or the memory interface 127. For example, theprocessor 122 may include a direct memory access (DMA) and output datausing the DMA.

The processor 122 includes an information collection unit 221 and aninformation addition unit 222. In other words, the processor 122collects status information of the storage device 100 (refer to FIG. 1)and outputs the collected status information via the host interface 125.

In an exemplary embodiment of the inventive concept, the processor 122may control the memory controller 120 using codes. The processor 122 mayload codes from a nonvolatile memory (e.g., a read only memory) includedin the memory controller 120. Or, the processor 122 may load codesreceived from the memory interface 127.

The RAM 123 is used as a work memory, a cache memory, or a buffer memoryof the processor 122. The RAM 123 stores codes or instructions that theprocessor 122 will execute. The RAM 123 stores data processed by theprocessor 122. The RAM 123 may include a static RAM (SRAM).

The ECC block 124 performs error correction. The ECC block 124 generatesparities for error correction based on data to be output to the memoryinterface 127. Data and parities may be output through the memoryinterface 127. The ECC block 124 corrects an error of data using dataand parities received through the memory interface 127.

The host interface 125 communicates with the external host according toa control of the processor 122. The host interface 125 may communicateusing at least one of various communication techniques such as UniversalSerial Bus (USB), Serial Advanced Technology Attachment (SATA), HighSpeed Interchip HSIC), SCSI, Firewire, Peripheral ComponentInterconnection (PCI), PCI express (PCIe), NonVolatile Memory express(NVMe), UFS, Secure Digital (SD), MultiMedia Card (MMC), embedded MMC(eMMC), and so on.

The memory interface 127 is configured to communicate with thenonvolatile memory 110 (refer to FIG. 1) according to a control of theprocessor 122.

FIG. 22 is a block diagram illustrating a nonvolatile memory 110according to an exemplary embodiment of the inventive concept. Referringto FIG. 22, the nonvolatile memory 110 includes a memory cell array 111,an address decoder circuit 113, a page buffer circuit 115, a datainput/output circuit 117, and a control logic circuit 119.

The memory cell array 111 includes a plurality of memory blocks BLK1 toBLKz, each of which has a plurality of memory cells. Each memory blockis connected to the address decoder circuit 113 through at least onestring selection line SSL, a plurality of word lines WL, and at leastone ground selection line GSL. The memory cell array 111 is connected tothe page buffer circuit 115 through a plurality of bit lines BL. Thememory blocks BLK1 to BLKz may be connected in common to the pluralityof bit lines BL. Memory cells of the memory blocks BLK1 to BLKz may havethe same structure, or not. For example, the first memory block BLK1 mayhave single level cell (SLC) memory cells, the second memory block BLK2may have multi level cell (MLC) memory cells, the third memory blockBLK3 may have tri level cell (TLC) memory cells and the fourth memoryblock BLK4 may have quad level cell (QLC) memory cells.

The address decoder circuit 113 is connected to the memory cell array111 through a plurality of ground selection lines GSL, the plurality ofword lines WL, and a plurality of string selection lines SSL. Theaddress decoder circuit 113 operates according to a control of thecontrol logic circuit 119. The address decoder circuit 113 receives anaddress from the memory controller 120 (refer to FIG. 1). The addressdecoder circuit 113 decodes an input address ADDR and controls voltagesto be applied to the word lines WL according to the decoded address. Forexample, at a programming, the address decoder circuit 113 applies apass voltage to the word lines WL according to a control of the controllogic circuit 119. At the programming, the address decoder circuit 113further applies a program voltage to a word line, selected by an addressADDR, from among the word lines WL according to a control of the controllogic circuit 119.

The page buffer circuit 115 is connected to the memory cell array 111through the bit lines BL. The page buffer circuit 115 is connected tothe data input/output circuit 117 through a plurality of data lines DL.The page buffer circuit 115 operates according to a control of thecontrol logic circuit 119.

The page buffer circuit 115 holds data to be programmed at memory cellsof the memory cell array 111 or data read from the memory cells of thememory cell array 111. During a program operation, the page buffercircuit 115 stores data to be stored in memory cells. The page buffercircuit 115 biases the plurality of bit lines BL based on the storeddata. The page buffer circuit 115 functions as a write driver at aprogram operation. During a read operation, the page buffer circuit 115senses voltages on the bit lines BL and stores sensing results. The pagebuffer circuit 115 functions as a sense amplifier at a read operation.

The data input/output circuit 117 is connected to the page buffercircuit 115 through the data lines DL. The data input/output circuit 117exchanges data DATA with the memory controller 120 (refer to FIG. 1).

The data input/output circuit 117 temporarily stores data, which thememory controller 120 provides, and transfers the stored data to thepage buffer circuit 115. The data input/output circuit 117 temporarilystores data transferred from the page buffer circuit 115 and transfersthe stored data to the memory controller 120. The data input/outputcircuit 117 functions as a buffer memory.

The control logic circuit 119 receives a command CMD from the memorycontroller 120. The control logic circuit 119 decodes the receivedcommand and controls an overall operation of the nonvolatile memory 110according to the decoded command. The control logic circuit 119 furtherreceives a variety of control signals and voltages from the memorycontroller 120 (refer to FIG. 1).

FIG. 23 is a circuit diagram illustrating a memory block BLKa accordingto an exemplary embodiment of the inventive concept. In FIG. 23, thereis illustrated one BLKa of a plurality of memory blocks BLK1 to BLKz ofthe memory cell array 111 shown in FIG. 22.

Referring to FIG. 23, the memory block BLKa includes a plurality ofstrings SR, which are connected to a plurality of bit lines BL1 to BLn,respectively. Each string SR contains a ground selection transistor GST,memory cells MC, and a string selection transistor SST.

In each string SR, the ground selection transistor GST is connectedbetween the memory cells MC and a common source line CSL. The groundselection transistors GST of the strings SR are connected in common tothe common source line CSL.

In each string SR, the string selection transistor SST is connectedbetween the memory cells MC and a bit line BL. The string selectiontransistors SST of the strings SR are connected to a plurality of bitlines BL1 to BLn, respectively.

In each string SR, the plurality of memory cells MC are connectedbetween the ground selection transistor GST and the string selectiontransistor SST. In each string SR, the plurality of memory cells MC areconnected in series.

In the strings SR, memory cells MC having the same height from thecommon source line CSL are connected in common to a word line. Thememory cells MC of the strings SR are connected to a plurality of wordlines WL1 to WLm.

FIG. 24 is a circuit diagram illustrating a memory block BLKb accordingto an exemplary embodiment of the inventive concept. Referring to FIG.24, the memory block BLKb includes a plurality of cell strings CS11 toCS21 and CS12 to CS22. The plurality of cell strings CS11 to CS21 andCS12 to CS22 are arranged along a row direction and a column directionand form rows and columns.

For example, the cell strings CS11 and CS12 arranged along the rowdirection form a first row, and the cell strings CS21 and CS22 arrangedalong the row direction form a second row. The cell strings CS11 andCS21 arranged along the column direction form a first column, and thecell strings CS12 and CS22 arranged along the column direction form asecond column.

The cell transistors include ground selection transistors GSTa and GSTb,memory cells MC1 to MC6, and string selection transistors SSTa and SSTb.The ground selection transistors GSTa and GSTb, memory cells MC1 to MC6,and string selection transistors SSTa and SSTb of each cell string arestacked in a height direction perpendicular to a plane (e.g., a planeabove a substrate of the memory block BLKb) on which the cell stringsCS11 to CS21 and CS12 to CS22 are arranged in rows and columns.

Each cell transistor may be formed of a charge trap type cell transistorof which a threshold voltage is varied according to the amount of chargetrapped in its insulation film.

Lowermost ground selection transistors GSTa are connected in common to acommon source line CSL.

The ground selection transistors GSTa and GSTb of the plurality of cellstrings CS11 to CS21 and CS12 to CS22 are connected in common to aground selection line GSL.

In an exemplary embodiment of the inventive concept, ground selectiontransistors at the same height (or, order from the substrate) may beconnected to the same ground selection line, and ground selectiontransistors at a different height (or, order from the substrate) may beconnected to different a ground selection line. For example, the groundselection transistors GSTa with a first height may be connected incommon to a first ground selection line, and the ground selectiontransistors GSTb with a second height may be connected in common to asecond ground selection line.

In an exemplary embodiment of the inventive concept, ground selectiontransistors in the same row may be connected to the same groundselection line, and ground selection transistors in a different row maybe connected to a different ground selection line. For example, theground selection transistors GSTa and GSTb of the cell strings CS11 andCS12 in the first row are connected in common to a first groundselection line, and the ground selection transistors GSTa and GSTb ofthe cell strings CS21 and CS22 in the second row are connected in commonto a second ground selection line.

Word lines are in common connected to memory cells that are placed atthe same height (or, order) from the substrate (or, the ground selectiontransistors GST). Memory cells that are placed at different heights (or,orders) from the substrate (or, the ground selection transistors GST)are connected to different word lines WL1 to WL6. For example, thememory cells MC1 are connected in common to the word line WL1, thememory cells MC2 are connected in common to the word line WL2, and thememory cells MC3 are connected in common to the word line WL3. Thememory cells MC4 are connected in common to the word line WL4, thememory cells MC5 are connected in common to the word line WL5, and thememory cells MC6 are connected in common to the word line WL6.

In first string selection transistors SSTa, having the same height (or,order), of the cell strings CS11 to CS21 and CS12 to CS22, the firststring selection transistors SSTa in different rows are connected todifferent string selection lines SSL1 a and SSL2 a. For example, thefirst string selection transistors SSTa of the cell strings CS11 andCS12 are connected in common to the string selection line SSL1 a, andthe first string selection transistors SSTa of the cell strings CS21 andCS22 are connected in common to the string selection line SSL2 a.

In second string selection transistors SSTb, having the same height (or,order), of the cell strings CS11 to CS21 and CS12 to CS22, the secondstring selection transistors SSTb in different rows are connected to thedifferent string selection lines SSL1 b and SSL2 b. For example, thesecond string selection transistors SSTb of the cell strings CS11 andCS12 are connected in common to the string selection line SSL1 b, andthe second string selection transistors SSTb of the cell strings CS21and CS22 are connected in common to the string selection line SSL2 b.

In other words, cell strings in different rows may be connected todifferent string selection lines. String selection transistors, havingthe same height (or, order), of cell strings in the same row areconnected to the same string selection line. String selectiontransistors, having different heights (or, orders), of cell strings inthe same row are connected to different string selection lines.

In an exemplary embodiment of the inventive concept, string selectiontransistors of cell strings in the same row are connected in common to astring selection line. For example, string selection transistors SSTa ofthe cell strings CS11 and CS12 in the first row are connected in commonto the string selection line SSL1 a, and string selection transistorsSSTa of the cell strings CS21 and CS22 in the second row are connectedin common to the string selection line SSL2 a.

Columns of the cell strings CS11 to CS21 and CS12 to CS22 are connectedto different bit lines BL1 and BL2, respectively. For example, stringselection transistors SSTb of the cell strings CS11 and CS21 in thefirst column are connected in common to the bit line BL1, and stringselection transistors SSTb of the cell strings CS12 and CS22 in thesecond column are connected in common to the bit line BL2.

The memory block BLKb shown in FIG. 24 is exemplary. However, theinventive concept is not limited thereto. For example, the number ofrows of cell strings may increase or decrease. As the number of rows ofcell strings is changed, the number of string or ground selection linesand the number of cell strings connected to a bit line may also bechanged.

The number of columns of cell strings may increase or decrease. As thenumber of columns of cell strings is changed, the number of bit linesconnected to columns of cell strings and the number of cell stringsconnected to a string selection line may also be changed.

A height of the cell strings may increase or decrease. For example, thenumber of ground selection transistors, memory cells, or stringselection transistors that are stacked in each cell string may increaseor decrease.

In an exemplary embodiment of the inventive concept, a write and a readoperation may be performed by row. For example, the cell strings CS11 toCS21 and CS12 to CS22 may be selected by row through the stringselection lines SSL1 a, SSL1 b, SSL2 a, and SSL2 b.

In a selected row of the cell strings CS11 to CS21 and CS12 to CS22, awrite or a read operation may be performed by word line. In a selectedrow of the cell strings CS11 to CS21 and CS12 to CS22, memory cellsconnected to a selected word line may be programmed.

FIG. 25 is a block diagram illustrating a storage device 300 accordingto an exemplary embodiment of the inventive concept. Referring to FIG.25, the storage device 300 includes a nonvolatile memory 310, a memorycontroller 320, and a memory 330. The storage device 300 is differentfrom the storage device 100 described with reference to FIG. 1 in thatit further includes the memory 330 outside of the nonvolatile memory 310and the memory controller 330.

The memory 330 may include a variety of random access memories such as,but not limited to, an SRAM, a dynamic RAM, a synchronous DRAM, a PRAM,an MRAM, an RRAM, an FeRAM, and so on.

The memory controller 320 may use the memory 330 as a buffer memory, acache memory, or a work memory. The memory controller 320 stores datareceived from a host device in the memory 330 and writes data stored inthe memory 330 at the nonvolatile memory 310. The memory controller 320stores data read from the nonvolatile memory 310 in the memory 330 andoutputs data stored in the memory 330 to the host device. The memorycontroller 320 stores data read from the nonvolatile memory 310 in thememory 330 and writes data stored in the memory 330 back to thenonvolatile memory 310.

The memory controller 320 stores data or codes necessary to manage thenonvolatile memory 310 in the memory 330. For example, the memorycontroller 320 reads data or codes necessary to manage the nonvolatilememory 310 from the nonvolatile memory 310 and drives it on the memory330.

The storage device 300 may be a solid state drive (SSD), a memory card,or an embedded memory.

As illustrated in FIG. 25, the memory controller 320 includes aninformation collection unit 221 and an information addition unit 222.The information collection unit 221 and the information addition unit222 may be configured substantially the same as described above withreference to FIG. 1, for example.

FIG. 26 is a block diagram illustrating a computing device 1000according to an exemplary embodiment of the inventive concept. Referringto FIG. 26, the computing device 1000 includes a processor 1100, a RAM1200, a storage device 1300, a modem 1400, and a user interface 1500.

The processor 1100 controls an overall operation of the computing device1000 and performs a logical operation. The processor 1100 is formed of asystem-on-chip (SoC). The processor 1100 may be a general purposeprocessor, a specific-purpose processor, or an application processor.

The RAM 1200 communicates with the processor 1100. The RAM 1200 may be aworking memory of the processor 1100 or the computing device 1000. Theprocessor 1100 stores codes or data in the RAM 1200 temporarily. Theprocessor 1100 executes codes using the RAM 1200 to process data. Theprocessor 1100 executes a variety of software, such as, but not limitedto, an operating system and an application, using the RAM 1200. Theprocessor 1100 controls an overall operation of the computing device1000 using the RAM 1200. The RAM 1200 may include a volatile memory suchas, but not limited to, an SRAM, a DRAM, an SDRAM, and so on or anonvolatile memory such as, but not limited to, a PRAM, an MRAM, anRRAM, an FeRAM, and so on.

The storage device 1300 communicates with the processor 1100. Thestorage device 1300 is used to store data for a long time. In otherwords, the processor 110 stores data, which is to be stored for a longtime, in the storage device 1300. The storage device 1300 stores a bootimage for driving the computing device 1000. The storage device 1300stores source codes of a variety of software, such as an operatingsystem and an application. The storage device 1300 stores data that isprocessed by a variety of software, such as an operating system and anapplication.

In an exemplary embodiment of the inventive concept, the processor 1100drives a variety of software, such as an operating system and anapplication, by loading source codes stored in the storage device 1300onto the RAM 1200 and executing codes loaded onto the RAM 1200. Theprocessor 1100 loads data stored in the storage device 1300 onto the RAM1200 and processes data loaded onto the RAM 1200. The processor 1100stores data, to be retained for a long time, of data stored in the RAM1200 in the storage device 1300.

The storage device 1300 includes a nonvolatile memory, such as, but notlimited to, a flash memory, a PRAM, an MRAM, an RRAM, an FeRAM, and soon.

The modem 1400 communicates with an external device according to acontrol of the processor 1100. For example, the modem 1400 communicateswith the external device in a wired or wireless manner. The modem 1400may communicate with the external device, based on at least one ofwireless communications techniques such as Long Term Evolution (LTE),Worldwide Interoperability for Microwave Access (WiMax), Global Systemfor Mobile communication (GSM), Code Division Multiple Access (CDMA),Bluetooth, Near Field Communication (NFC), WiFi, Radio FrequencyIdentification (RFID), and so on. The modem 1400 may communicate withthe external device, based on at least one of wired communicationstechniques such as USB, SATA, HSIC, SCSI, Firewire, PCI, PCIe, NVMe,UFS, SD, Secure Digital Input Output (SDIO), Universal AsynchronousReceiver Transmitter (UART), Serial Peripheral Interface (SPI), HighSpeed SPI (HS-SPI), RS232, Inter-integrated Circuit I2C), HS-I2C,Integrated-interchip Sound (I2S), Sony/Philips Digital Interface Format(S/PDIF), MMC, eMMC, and so on.

The user interface 1500 communicates with a user according to a controlof the processor 1100. For example, the user interface 1500 may includeuser input interfaces such as a keyboard, a keypad, a button, a touchpanel, a touch screen, a touch pad, a touch ball, a camera, amicrophone, a gyroscope sensor, a vibration sensor, and so on. The userinterface 1500 may further include user output interfaces such as aliquid crystal display (LCD), an Organic Light Emitting Diode (OLED)display device, an Active Matrix OLED (AMOLED) display device, an LED, aspeaker, a motor, and so on.

The storage device 1300 may include a storage device 100 or 300described with reference to FIGS. 1 to 24. In other words, the storagedevice 1300 adds status information to response data to transmit thestatus information and response data to the processor 1100.

The processor 1100 controls the storage device 1300 using the statusinformation from the storage device 1300. For example, the processor1100 may perform operations associated with the storage device 1300,such as power control, lifetime control, and so on.

While the inventive concept has been described with reference toexemplary embodiments thereof, it will be apparent to those skilled inthe art that various changes and modifications may be made theretowithout departing from the spirit and scope of the present inventiveconcept as defined by the claims.

1. An operation method of a storage device which includes a nonvolatilememory and a memory controller configured to control the nonvolatilememory, the operation method comprising: receiving a request; performingan operation corresponding to the received request; generating responsedata corresponding to the performed operation, wherein the response dataincludes information on the performed operation; and outputting theresponse data, wherein status information is added to and output withthe response data, wherein the status information includes informationon a status of the storage device.
 2. The operation method of claim 1,wherein collection of the status information is independent of thereceived request and the performed operation.
 3. The operation method ofclaim 1, wherein the response data and the status information aretransferred using a format of Universal Flash Storage ProtocolInformation Unit (UPIU).
 4. The operation method of claim 3, wherein thestatus information is transferred using at least one field of 16^(th) to31^(st) fields of a response UPIU.
 5. The operation method of claim 3,wherein the status information is transferred using at least one fieldof 4^(th) to 7^(th), 9^(th), and 20^(th) to 31^(st) fields of a data outUPIU.
 6. The operation method of claim 3, wherein the status informationis transferred using at least one field of 20^(th) to 31^(st) fields ofa ready to transfer UPIU.
 7. The operation method of claim 3, whereinthe status information is transferred using at least one field of20^(th) to 31^(st) fields of a task management response UPIU.
 8. Theoperation method of claim 3, wherein the status information istransferred using at least one field of 28^(th) to 31^(st) fields of aquery response UPIU.
 9. The operation method of claim 3, wherein thestatus information is transferred using at least one field of 16^(th),17^(th), and 20^(th) to 27^(th) fields of a query response UPIU.
 10. Theoperation method of claim 3, wherein the status information istransferred using at least one field of 16^(th) to 19^(th) and 24^(th)to 27^(th) fields of a query response UPIU.
 11. The operation method ofclaim 3, wherein the status information is transferred using at leastone field of 16^(th) to 22^(nd) and 24^(th) to 27^(th) fields of a queryresponse UPIU.
 12. The operation method of claim 3, wherein the statusinformation is transferred using at least one field of 13^(th) to27^(th) fields of a query response UPIU.
 13. The operation method ofclaim 3, wherein the status information is transferred using at leastone field of 12^(th) to 31^(th) fields of a NOP IN UPIU.
 14. Theoperation method of claim 1, wherein the status information includespower-control information of the storage device.
 15. The operationmethod of claim 14, wherein the status information further includesinformation on a time when the storage device enters a power-savingmode.
 16. A storage device, comprising: a nonvolatile memory; and amemory controller configured to control the nonvolatile memory, whereinthe memory controller is further configured to collect statusinformation including information on a status of the nonvolatile memoryor the memory controller, and wherein if an access request is receivedfrom an external device, the memory controller is configured to performthe access request, add the status information to response dataincluding an execution result of the access request to generate firstdata, and output the first data to the external device.
 17. A computingsystem, comprising: a storage device; and a host device configured totransmit a request to the storage device to control the storage device,write data at the storage device or read data from the storage device,wherein the storage device is configured to collect status informationincluding information on a status of the storage device, and wherein thestorage device is further configured to receive the request, perform thereceived request, add the status information to response data includingan execution result of the received request to generate first data, andoutput the first data to the host device.
 18. The computing system ofclaim 17, wherein the storage device is further configured to insert afirst type of status information at a first location in a data formatincluding the response data, and wherein the host device is furtherconfigured to extract the first type of status information from thefirst location of the data format.
 19. The computing system of claim 17,wherein the storage device is further configured to insert the statusinformation and flag information indicating a type of the statusinformation in a data format including the response data, wherein thehost device is further configured to extract the status informationusing the flag information of the status information, and wherein theflag information is inserted at a predetermined location in the dataformat.
 20. The computing system of claim 17, wherein the storage deviceis further configured to insert the status information and mapinformation indicating a location and a type of the status informationin a data format including the response data, wherein the host device isfurther configured to extract the status information using the mapinformation, and wherein the map information is inserted at apredetermined location in the data format. 21-25. (canceled)